ADP5042
Data Sheet
Rev. A | Page 22 of 32
Watchdog Status Indicator
In addition to the dual watchdog function, the ADP5042
features a watchdog status monitor available on the WSTAT pin.
This pin can be queried by the external processor to determine
the origin of a reset. WSTAT is an open-drain output.
WSTAT outputs a logic level depending on the condition that
has generated a reset. WSTAT is forced low if the reset was
generated because of a Watchdog 2 timeout. WSTAT is pulled
high, through external pull-up, for any other reset cause (Watchdog
1 timeout, power failure or monitored voltage below threshold).
The status monitor is automatically cleared (set to logic level
high) 10 seconds after the nRSTO low to high transition (t
WDCLEAR
),
processor firmware must be designed being able to read the
WSTAT flag before tWDCLEAR expiration after a Watchdog 2 reset.
The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after nRSTO low to high transition. In this
situation, WSTAT maintains the previous state (see state flow in
Figure 60).
The external processor can further distinguish a reset caused by
a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.
Table 10 shows the possible watchdog decoded statuses.
Table 10. Watchdog Status Decoding
WSTAT
RAM CHECKSUM
RESET ORIGIN
High
Failed
Power failure
High
Ok
Watchdog 1
Low
Don't care
Watchdog 2
NO POWER APPLIED TO AVIN.
ALL REGULATORS AND SUPERVISORY
TURNED OFF
NO POWER
POR
STANDBY
WSTAT = HIGH
WSTAT = HIGH
RESET
NORMAL
WSTAT = LOW
AVIN < VUVLO
ALL ENx = LOW
AVIN > VUVLO
TRANSITION
STATE
TRANSITION
STATE
TRANSITION
STATE
END OF POR
WSTAT
TIMEOUT
(t
WDCLEAR
)
WSTAT = 1
TRANSITION
STATE
ALL REGULATORS AND
SUPERVISOR ACTIVATED
WDOG2
TIMEOUT
(t
WD2
)
WSTAT = 0
END OF (t
POFF
)
PULSE
WDOG1 TIMEOUT
(t
WD1
) AND
WSTAT TIMEOUT
WSTAT = 1
WDOG1 TIMEOUT
(t
WD1
)
ALL ENx = HIGH
ACTIVE
POWER OFF
RESET SHORT
AVIN < VUVLO
END OF RESET
PULSE (t
RP2
)
INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED
AVIN < VUVLO
VIN < VUVLO
VMON < VTH
END OF RESET
PULSE (t
RP1
)
Figure 60. ADP5042 State Flow
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